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74LCX646
LOW VOLT. CMOS OCTAL BUS TRANSCEIVER/REGISTER WITH 5 VOLT TOLERANT INPUTS AND OUTPUTS(3-STATE)
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5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED : tPD = 7.0 ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 646 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V
SOP
TSSOP
ORDER CODES
PACKAGE SOP TSSOP TUBE 74LCX646M1R T&R 74LCX646RM13TR 74LCX646TTR
DESCRIPTION The 74LCX646 is a low voltage CMOS OCTAL BUS TRANSCEIVER AND REGISTER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. PIN CONNECTION AND IEC LOGIC SYMBOLS
This device consists of bus transceiver circuits with 3 state, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into register on the low to high transition of the appropriate clock pin (Clock AB or Clock BA). Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select controls (Select AB select BA) can multiplex stored and real time (transparent mode) data. The direction control determines which bus will receive data when enable G is active (low). In the isolation mode
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(enable G high), "A" data may be stored in one register and/or "B" data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. It has same speed performance at 3.3V than 5V INPUT AND OUTPUT EQUIVALENT CIRCUIT AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
PIN DESCRIPTION
PIN No 1 2 3 4, 5, 6, 7, 8, 9, 10, 11 20, 19, 18, 17, 16, 15, 14, 13 21 22 23 12 24 SYMBOL CLOCK AB (CAB) SELECT AB (SAB) DIR A1 to A8 B1 to B8 G SELECT BA (SBA) CLOCK BA (CBA) GND VCC NAME AND FUNCTION A to B Clock Input (LOW to HIGH, Edge-Triggered) Select A to B Source Input Direction Control Input A Data Inputs/Outputs B Data Inputs/Outputs Output Enable Input (Active LOW) Select B to A Source Input B to A Clock Input (LOW to HIGH, Edge Triggered) Ground (0V) Positive Supply Voltage
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TRUTH TABLE
G DIR CAB CBA SAB SBA X H X X X X X X A INPUTS Z B INPUTS Z FUNCTION
X
X* X*
L L H H
X X X X
L
H X X* X*
X* X* L L X* X*
X
X X
L L H H
X
X X
Both the A bus and the B bus are inputs The Output functions of the A and B bus are disabled Both the A and B bus are used as inputs to the internal INPUTS INPUTS flip-flops. Data at the bus will be stored on low to high transition of the clock inputs. INPUTS OUTPUTS The A bus are inputs and the B bus are outputs L L The data at the A bus are displayed at the B bus H H L L The data at the A bus are displayed at the B bus. The data of the A bus are stored to internal flip-flop on low H H to high transition of the clock pulse The data stored to the internal flip-flop are displayed at X Qn the B bus. L L The data at the A bus are stored to the internal flip-flop on low to high transition of the clock pulse. The states H H of the internal flip-flops output directly to the B bus. OUTPUTS INPUTS The B bus are inputs and the A bus are outputs. L L The data at the B bus are displayed at the A bus H H L L The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flip-flop on H H low to high transition of the clock pulse. The data stored to the internal flip-flops are displayed Qn X at the A bus L L The data at the B bus are stored to the internal flip-flop on low to high transition of the clock pulse. The states H H of the internal flip-flops output directly to the A bus.
X : Don't Care Z : High Impedance Qn : The data stored to the internal flip-flops by most recent low to high transition of the clock inputs * : The data at the A and B bus will be stored to the internal flip-flops on every low to high transition of the clock inputs.
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LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
TIMING CHART
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ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO VO IIK IOK IO ICC IGND Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (OFF State) DC Output Voltage (High or Low State) (note 1) DC Input Diode Current DC Output Diode Current (note 2) DC Output Current DC Supply Current per Supply Pin DC Ground Current per Supply Pin Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 50 - 50 50 100 100 -65 to +150 300 Unit V V V V mA mA mA mA mA C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO VO IOH, IOL IOH, IOL Top dt/dv Supply Voltage (note 1) Input Voltage Output Voltage (OFF State) Output Voltage (High or Low State) High or Low Level Output Current (VCC = 3.0 to 3.6V) High or Low Level Output Current (VCC = 2.7V) Operating Temperature Input Rise and Fall Time (note 2) Parameter Value 2.0 to 3.6 0 to 5.5 0 to 5.5 0 to VCC 24 12 -55 to 125 0 to 10 Unit V V V V mA mA C ns/V
1) Truth Table guaranteed: 1.5V to 3.6V 2) VIN from 0.8V to 2V at VCC = 3.0V
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DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) -40 to 85 C Min. 2.0 2.7 to 3.6 0.8 2.7 to 3.6 2.7 3.0 VOL Low Level Output Voltage 2.7 to 3.6 2.7 3.0 II Ioff IOZ Input Leakage Current Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ICC incr. per Input 2.7 to 3.6 0 2.7 to 3.6 IO=-100 A IO=-12 mA IO=-18 mA IO=-24 mA IO=100 A IO=12 mA IO=16 mA IO=24 mA VI = 0 to 5.5V VI or VO = 5.5V VI = VIH or VIL VO = 0 to VCC VI = VCC or GND VI or VO= 3.6 to 5.5V VIH = VCC - 0.6V VCC-0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5 10 5 10 10 500 VCC-0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5 10 5 10 10 500 A A A A A V V 0.8 V Max. Value -55 to 125 C Min. 2.0 Max. V Unit
VIH VIL VOH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
ICC ICC
2.7 to 3.6 2.7 to 3.6
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 3.3 CL = 50pF VIL = 0V, VIH = 3.3V Value TA = 25 C Min. Typ. 0.8 -0.8 Max. V Unit
VOLP VOLV
Dynamic Low Level Quiet Output (note 1)
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state.
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AC ELECTRICAL CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 50 50 50 500 500 500 2.5 2.5 2.5 50 500 2.5 50 50 50 50 500 500 500 500 2.5 2.5 2.5 2.5 50 500 2.5 50 500 2.5 CL (pF) RL () ts = t r (ns) -40 to 85 C Min. 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 1.5 1.5 4.0 3.3 150 1.0 Max. 9.5 8.5 8.0 7.0 9.5 8.5 9.5 8.5 9.5 8.5 Value -55 to 125 C Min. 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 1.5 1.5 4.0 3.3 150 1.0 ns MHz ns ns Max. 9.5 8.5 8.0 7.0 9.5 8.5 9.5 8.5 9.5 8.5 ns ns ns ns ns ns Unit
tPLH tPHL
tPLH tPHL
tPLH tPHL
tPZL tPZH tPLZ tPHZ tS
Propagation Delay Time (CAB or CBA to An or Bn) Propagation Delay Time (An to Bn or Bn to An) Propagation Delay Time (SAB or SBA to An or Bn) Output Enable Time (G, DIR to An, Bn) Output Disable Time (G, DIR to An, Bn) Setup Time, HIGH or LOW level Data to CAB, CBA Hold Time, HIGH or LOW level Data to CAB, CBA CAB, CBA Pulse Width, HIGH or LOW Clock Pulse Frequency Output To Output Skew Time (note1, 2)
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tW
fMAX tOSLH tOSHL
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - t PLHn|, tOSHL = | tPHLm - tPHLn|) 2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 3.3 3.3 3.3 VIN = 0 to VCC VIN = 0 to VCC fIN = 10MHz VIN = 0 or VCC Value TA = 25 C Min. Typ. 6 10 37 Max. pF pF pF Unit
CIN CI/O CPD
Input Capacitance I/O Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/8 (per circuit)
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TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL = 50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 500 or equivalent RT = ZOUT of pulse generator (typically 50)
SWITCH Open 6V GND
WAVEFORM 1 : PROPAGATION DELAYS, SAB, SBA, An, Bn, TIMES (f=1MHz; 50% duty cycle)
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WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
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WAVEFORM 3 : SETUP AND HOLD TIME, CAB, CBA MAXIMUM FREQUENCY (f=1MHz; 50% duty cycle)
WAVEFORM 4 : PULSE WIDTH (f=1MHz; 50% duty cycle)
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SO-24 MECHANICAL DATA
mm. DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L S 7.40 0.50 15.20 10.00 1.27 13.97 7.60 1.27 8 (max.) 0.291 0.020 15.60 10.65 0.35 0.23 0.5 45 (typ.) 0.598 0.393 0.050 0.550 0.300 0.050 0.614 0.419 0.1 TYP MAX. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. TYP. MAX. 0.104 0.008 0.096 0.019 0.012 inch
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TSSOP24 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.50 0.19 0.09 7.7 6.25 4.3 0.65 BSC 8 0.70 0 0.020 0.05 0.9 0.30 0.20 7.9 6.5 4.5 0.0075 0.0035 0.303 0.246 0.169 0.0256 BSC 8 0.028 TYP MAX. 1.1 0.15 0.002 0.035 0.0118 0.0079 0.311 0.256 0.177 MIN. TYP. MAX. 0.043 0.006 inch
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PIN 1 IDENTIFICATION
1
7047476A
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com
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